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FEMTOCLOCKS- CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
ICS844002I-01 Features
* * * * * * * *
Two differential LVDS outputs Selectable crystal oscillator interface or single-ended LVCMOS/LVTTL input Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz VCO range: 560MHz - 680MHz RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.41ps (typical) Full 2.5V supply mode -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
General Description
The ICS844002I-01 is a 2 output LVDS Synthesizer optimized to generate Ethernet reference clock HiPerClockSTM frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from IDT. Using a 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz and 62.5MHz. The ICS844002I-01 uses IDT's 3rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS844002I-01 is packaged in a small 20-pin TSSOP package.
ICS
Block Diagram
F_SEL[1:0] Pulldown PLL_SEL Pulldown F_SEL[1:0] 0 0 /4 0 1 /5 1 0 /10 1 1 not used 2 Q0 1 Q0
Pin Assignment
nc VDDO Q0 Q0 MR PLL_SEL nc VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDO Q1 Q1 GND nc XTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1
REF_CLK Pulldown
25MHz
1
XTAL_IN
OSC
XTAL_OUT XTAL_SEL Pulldown
0
Phase Detector
VCO 625MHz
(w/25MHz Reference)
0
Q1 Q1
M = 25 (fixed)
MR Pulldown
ICS844002I-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View
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Table 1. Pin Descriptions
Number 1, 7 2, 20 3, 4 Name nc VDDO Q0, Q0 Power Output Type Unused Description No connect. Output supply pins. Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs Qx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and REF_CLK as input to the dividers. When LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pins. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown Pulldown Non-inverting differential clock input. Selects between crystal or REF_CLK inputs as the PLL Reference source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. No connect. Power supply ground. Differential output pair. LVDS interface levels.
5
MR
Input
Pulldown
6 8 9, 11 10 12, 13 14 15 16 17 18, 19
PLL_SEL VDDA FSEL0, F_SEL1 VDD XTAL_OUT, XTAL_IN REF_CLK XTAL_SEL nc GND Q1, Q1
Input Power Input Power Input Input Input Unused Power Output
Pulldown
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 10mA 15mA 73.2C/W (0 lfpm) -65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 2.5V 5%, TA = -40C to 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 Maximum 2.625 2.625 2.625 98 12 98 Units V V V mA mA mA
Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 2.5V 5%, TA = -40C to 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current REF_CLK, MR, FSEL0, FSEL1, PLL_SEL, XTAL_SEL REF_CLK, MR, FSEL0, FSEL1, PLL_SEL, XTAL_SEL Test Conditions 2.5V 2.5V VDD = VIN = 2.625V Minimum 1.7 -0.3 Typical Maximum VDD + 0.3 0.7 150 Units V V A
IIL
Input Low Current
VDD = 2.625V, VIN = 0V
-5
A
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Table 3C. LVDS DC Characteristics, VDD = VDDA = VDDO = 2.5V 5%, TA = -40C to 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 0.7 Test Conditions Minimum 240 40 1.1 50 1.5 Typical Maximum 550 Units mV mV V mV
Table 4. Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 22.4 Test Conditions Minimum Typical Fundamental 25 27.2 50 7 1 MHz Maximum Units
pF mW
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = VDDA = VDDO = 2.5V 5%, TA = -40C to 85C
Parameter Symbol fOUT tsk(o) tjit(O) tR / tF odc Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz - 20MHz) RMS Phase Jitter, (Random); NOTE 3 Output Rise/Fall Time Output Duty Cycle 125MHz, (1.875MHz - 20MHz) 62.5MHz, (1.875MHz - 20MHz) 20% to 80% 250 48 Test Conditions FSEL[1:0] = 00 FSEL[1:0] = 01 FSEL[1:0] = 10 Minimum 140 112 56 5 0.41 0.44 0.47 550 52 Typical Maximum 170 136 68 20 Units MHz MHz MHz ps ps ps ps ps %
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
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Typical Phase Noise at 156.25MHz
-10 -20 -30 -40 -50 -60 dBc Hz -70 -80 -90 -100 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.41ps (typical)
Noise Power
-110 -120 -130 -140
Raw Phase Noise Data
-160 -170 -180 -190 1k 10k 100k
-150
Phase Noise Result by adding a Ethernet filter to raw data
1M

0
Ehternet Filter
10M
100M
Offset Frequency (Hz)
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Parameter Measurement Information
SCOPE
3.3V5% POWER SUPPLY + Float GND -
SCOPE
2.5V5% POWER SUPPLY + Float GND -
VDD,
Qx
V VDDO DDA
VDD,
Qx
LVDS
nQx
V VDDO DDA
LVDS
nQx
3.3V Output Load AC Test Circuit
2.5V Output Load AC Test Circuit
Qx Qx
80%
Qy Qy
80% VOD
Clock Outputs tsk(o)
20% tR tF
20%
Output Skew
Output Rise/Fall Time
Q0, Q1 Q0, Q1
VDD out
t PW
PERIOD
odc =
t PW t PERIOD
x 100%
out
VOS/ VOS
Output Duty Cycle/Pulse Width/Period
Offset Voltage Setup
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t
DC Input
LVDS
ICS844002I-01 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
VDD

out
DC Input
LVDS
100
VOD/ VOD out
Differential Offset Voltage Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844002I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA pin.
2.5V VDD .01F VDDA .01F 10F 10
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Outputs: LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
REF_CLK INPUT
For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground.
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Crystal Input Interface
The ICS844002I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 22p X1 18pF Parallel Crystal XTAL_OUT C2 22p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
VDD
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
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2.5V LVDS Driver Termination
Figure 4 shows a typical termination for LVDS driver in characteristic impedance of 100 differential (50 single) transmission line environment. For buffer with multiple LVDS driver, it is recommended to terminate the unused outputs.
2.5V 2.5V 50
LVDS Driver R1 100
+
-
50
100 Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844002I-01. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS44002I-01 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. * * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 2.625V * (98mA + 12mA) = 288.75mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 2.625V * 98mA = 257.25mW
Total Power_MAX = 288.75mW + 257.25mW = 546mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.546W * 66.6C/W = 121.4C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
JA by Velocity Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 114.5C/W 73.2C/W 200 98.0C/W 66.6C/W 500 88.0C/W 63.5C/W
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Reliability Information
Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP
JA by Velocity Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 114.5C/W 73.2C/W 200 98.0C/W 66.6C/W 500 88.0C/W 63.5C/W
Transistor Count
The transistor count for ICS844002I-01 is: 2914
Package Outline and Package Dimension
Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 9. Ordering Information
Part/Order Number 844002AGI-01 844002AGI-01T 844002AGI-01LF 844002AGI-01LFT Marking ICS44002AI01 ICS44002AI01 ICS4002AI01L ICS4002AI01L Package 20 Lead TSSOP 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev Table T1 T3B Page 1 2 3 7 10 Description of Change Pin Assignment - correct pin 16 from VDD to nc. Pin Description Table - deleted pin 16 from VDD row. Added Pin 16 row, "nc". LVCMOS DC Characteristics Table - corrected IIL from -150A min. to -5A min. Parameter Measurement Information - corrected Output Rise/Fall Time diagram. Power Considerations - updated calculations. Date
C
9/28/07
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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